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Freescale Semiconductor /MK61F15WS /PDB0 /PO3DLY

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Interpret as PO3DLY

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DLY20DLY1

Description

Pulse-Out n Delay Register

Fields

DLY2

PDB Pulse-Out Delay 2
DLY1

PDB Pulse-Out Delay 1

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data